1. Field of the Invention
The present invention is directed to memory devices and, more particularly, to methods and circuits for reading information out of and writing information into the memory device.
2. Description of the Background
Computer designers are continually searching for faster memory devices that will permit the design of faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory devices such as dynamic random access memories (DRAMs), synchronous dynamic random access memories (SDRAMs), flash memories, etc. typically include a large number of memory cells arranged in one or more arrays, each array comprised of rows and columns. Each memory cell provides a location at which the processor can store and retrieve one bit of data, sometimes referred to as a memory bit or mbit. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1 shows, in part, a typical computer system architecture. A central processing unit (CPU) or processor 10 is connected to a processor bus 12, which in turn is connected to a system or memory controller 14. The memory controller 14 may be connected to an expansion bus 16. The memory controller 14 serves as interface circuitry between the processor 10 and a memory device 18. The processor 10 issues a command and an address which are received and translated by the memory controller 14. The memory controller 14 applies the translated command signals on a plurality of command lines 20 and the translated address on a plurality of address lines 22 to the memory device 18. These command signals are well known in the art and include, in the case of a DRAM, RAS (row address strobe), CAS (column address strobe), WE (write enable) and OE (output enable). A clock signal is also provided on CLK lines 24. Corresponding to the processor-issued command and address, data is transferred between the controller 14 and the memory 18 via datapath lines 26.
The memory 18 typically comprises a number of memory ranks 27, a representative one of which is illustrated in FIG. 2. In this example, the memory rank 27 is configured for a 64-bit system, having eight 8-bit memory circuits 28(0)–28(7). The command signals RAS, CAS and WE are applied to all memory circuits 28(0)–28(7) in the rank 27. In a memory 18 (FIG. 1) having additional ranks, separate CS command signals would be provided for each rank. Hence, the command signal CS is often referred to as a rank-specific command signal. The address bus 22 is connected to all the memory circuits 28(0)–28(7) in the rank 27 and to all other memory circuits (not shown) in all other ranks (not shown) of the memory 18. Hence, the address bus 22 is often referred to as globally connected.
A synchronous DRAM (SDRAM) is a memory device capable of sequentially accessing, by virtue of internal operations, a certain range of addresses at high speeds. In a typical SDRAM, a read/write rate of 100 Mbytes/sec or greater is possible. To achieve such speeds, the read/write of an SDRAM is performed in a burst mode. Burst mode is a mode of address access where data having the same row addresses are read or written continuously in blocks of 2, 4, or 8 bit words. In addition, the access for such words in the block is made by simply providing the start address of the block. Afterward, the remaining addresses are generated automatically in the SDRAM in accordance with its mode of operation: sequential or interleave. The mode of operation is determined by an address sequence from the CPU. Addresses for each burst address sequence method are generated, in the sequential mode, by addition of the burst start address and an output of an internal counter. In the interleave mode, the addresses are generated by an exclusive OR of the burst start address and an output of an internal counter. The same wrap mode is used for both read and write operations, with all column address bits used for both read and write operations.
As clock speeds increased above 200 MHz (i.e. RDRAM or SLDRAM), the core operation of the DRAM did not increase at the same rate. Therefore, the DRAMs completed the reads and writes on 4 or 8 words internally and then output the word sequentially onto the external bus. As entire groups of data words were being transferred, the least significant column addresses were no longer transmitted to the DRAM.
That solution works well for write data from a controller to the DRAM as it can be aligned to a cache fill. However, because a complete block of data words is transferred at the same time for reads, the most critical word is not always received first by the controller, which can add latency to the system. The need exists for a high clock rate DRAM memory supporting the block transfers of data words while delivering the most critical word first to the controller. Additional need exists for a communication protocol between the memory controller and the DRAM to support such a new feature.